The present invention relates to the testing of integrated circuits and, in particular, to a logic pattern implemented by a Built-In Self-Test (BIST) that fully tests static decoders (decoders comprised of static CMOS logic elements) in a compilable static random-access memory (SRAM) architecture.
Existing xe2x80x9cunique addressxe2x80x9d BIST logic patterns test the SRAM by accessing each memory cell in a sequential incrementing address or decrementing address pattern. These patterns are used because they are exhaustive in that they access every cell address in the design as well as being very easily implemented in an on-chip BIST circuit. For each cell access, a logic value is read, then the opposite logic value is written and read. Unfortunately, these patterns do not filly test the static address decoder logic inside the SRAM, as will become clear from the following.
A simple prior art three-bit static decoder, implemented as a three-input NAND (FIG. 1a) decoder in complementary MOS (CMOS) logic, is shown in FIG. 1b. Output Z of FIG. 1b is a logical xe2x80x9c0xe2x80x9d when inputs A0, A1, and A2 are all at a logical xe2x80x9c1xe2x80x9d. The output Z is a logic 1 value for all other combinations of the inputs. A traditional sequential addressing pattern, for the decoder of FIG. 1b, is shown in FIG. 2, where A0 is the least significant bit (LSB). As shown in the incrementing address sequence of FIG. 2, the only transitions that cause the output Z to change logical state are from cycle 7 to 8, (A), and from cycle 8 to 9, (B). All of the n-channel field effect transistors (NFETs) must be functional to cause Z to transition to a logical xe2x80x9c0xe2x80x9d. However, for the output Z to transition from a logical 0 to a logical 1, only one functional p-channel FET (PFET) is needed, as shown by transition (B). Either of the other two remaining PFETs could be xe2x80x9cstuck openxe2x80x9d and this test pattern would not detect them. The reason the xe2x80x9cstuck openxe2x80x9d fault would not be detected is described by example in the following paragraph.
Suppose PFET P2, as shown in FIG. 1a, is defective due to a xe2x80x9cstuck openxe2x80x9d fault and PFETS P0 and P1 function properly. During cycle 4, listed in the table of FIG. 2, the logic values assigned to bits A0-A2 will cause PFETS P0 and P1 to stop conducting current between their respective drain and source leads. In other words, P0 and P1 will become open circuited. PFET P2 is intended to conduct current, thereby allowing the higher potential rail voltage, less the small drain-to-source voltage drop, to develop on the output Z. However, because P2 has a xe2x80x9cstuck-openxe2x80x9d fault, the PFET does not conduct current between its drain and source and, therefore, cannot support the development of a voltage potential at output Z. This situation does not necessarily cause the output Z to transition to a logical 0 state, though. During cycle 3, output Z has a voltage potential representing a logical 1 and this potential will charge the parasitic capacitances of the FETs. The parasitic resistances of the FETs will not discharge the stored energy quickly enough to cause the output Z to reflect a logical 0, in some instances. In such an instance, only a conductive path between output Z and the lower potential rail voltage could discharge the stored energy sufficiently quickly to generate a logical 0 on output Z. During cycle 4, however, the NFET connected to A2, and in series with the two other NFETs, prevents the flow of current between the output Z and the lower potential rail. Therefore, the xe2x80x9cstuck openxe2x80x9d fault affecting P2 would not be detected by the test sequence shown in the table of FIG. 2. Similarly, a xe2x80x9cstuck openxe2x80x9d fault affecting any other PFET or any two PFETs may not be detected by the test sequence.
Again, for the three-input NAND gate, the decrementing address sequence of FIG. 3 shows that the output Z changes its logical state only during the transition from cycle 1 to cycle 2, (A), and from cycle 8 to cycle 9, (B). Transition (B) will fully test the NFETs, since all 3 NFETs are required to be functional for the output Z to change to a logical xe2x80x9c0.xe2x80x9d Transition (A) requires only one PFET (specifically device P0) to be functional for the output Z to change to a logical xe2x80x9c1xe2x80x9d state. Devices P1 and P2 could have xe2x80x9cstuck openxe2x80x9d faults and this test sequence would not detect them, for the same reason described in the preceding paragraph.
This problem also exists for a NOR decoder. A three bit NOR decoder is shown in FIGS. 4a and 4b. The output Z is a logic 1 value when inputs A0, A1, and A2 are all at logic 0 values. The output Z is a logic 0 value for all other combinations of the inputs. An ascending sequential addressing pattern is shown in FIG. 5, where A0 is the least significant bit (LSB). As shown in FIG. 5, the only transitions that cause the output Z to change logic states are from cycle 1 to 2, (A), and from cycle 8 to 9, (B). All three PFETs must be functional to transition the output Z from 0 to 1. In transition (A), the only NFET being tested is NO. A xe2x80x9cstuck-openxe2x80x9d fault in N1 or N2 will go undetected by this test. Again, for the descending pattern, only one NFET must be functional and either of the other two may have xe2x80x9cstuck-openxe2x80x9d faults, which would go undetected, as shown in FIG. 6. The reason these xe2x80x9cstuck openxe2x80x9d faults would not be detected is explained by example in the following paragraph.
Suppose NFET N2, as shown in FIG. 4a, is defective due to a xe2x80x9cstuck openxe2x80x9d fault and NFETS N0 and N1 function properly. During cycle 5, listed in the table of FIG. 5, the logic values assigned to bits A0-A2 will cause NFETS N0 and N1 to stop conducting current between their respective drain and source leads. In other words, N0 and N1 will become open circuited. NFET N2 is intended to conduct current, thereby allowing output Z to develop the voltage of the lower potential rail, plus the small drain-to-source voltage drop. However, because N2 has a xe2x80x9cstuck-openxe2x80x9d fault, the NFET does not conduct current between its drain and source and, therefore, cannot discharge the energy stored by the parasitic capacitances of the FETs quickly enough in some instances. This situation does not necessarily cause the output Z to transition to a logical 1 state, though. During cycle 4, output Z has a voltage potential representing a logical 0 and this potential determines the charge stored by the parasitic capacitances of the FETs attached to output Z. The PFETs connected to A0 and A1, and in series with PFET A2, prevent the flow of current between the output Z and the higher potential rail. As a result, the output Z will tend to maintain the logical 0 state since no conductive path exists to the higher potential rail. Therefore, the xe2x80x9cstuck openxe2x80x9d fault affecting N2 would not be detected by the test sequence shown in the table of FIG. 5.
The sequential addressing patterns (both the increment and decrement) do not test devices P1 and P2 in the NAND and devices N1 and N2 in the NOR. The traditional unique address pattern used during a self-test operation is sequential. However, during normal functional operation the SRAM is accessed randomly. It was shown above that the SRAM would pass a sequential pattern, generated by an on-chip BIST, even when certain decoder devices are failing. However, these failures may be exhibited in normal operation, resulting in non-functional customer hardware. Therefore, it is imperative that these xe2x80x9cstuck-openxe2x80x9d faults be detected during a manufacturing test.
Application specific integrated circuit (ASIC) products create a number of very unique concerns. The nature of ASIC products is such that unique circuit designs may be readily developed during the market-life of an ASIC technology library, with each design different from the rest and developed for a highly specific use. Also, the SRAMs, which appear in these ASIC chips, may be configured to the customers""size and area needs. Because of the large number of chip designs involved, the entire design-for-testability (DFT) flow is automated, with minimal manual intervention. Because each ASIC technology library contains several different SRAM architectures, a single test pattern is required that is generic enough to test various CMOS static decoder implementations, which may exist in these various SRAM architectures.
Also, a particular ASIC test methodology may use an on-chip MABIST (Multiple Array Built-In Self-Test) controller to self-test the SRAMs. The MABIST controller can be implemented as a state machine capable of producing a number of test controls and a set of test vectors that access the SRAMS.
The invention is drawn to a method and an apparatus that make use of the decoder addressing logic pattern, shown in FIGS. 7a-7c, to simulate multiple random accesses to an SRAM in order to solve the testability problems described above. Applying the logic pattern to the input lines of a static decoder allows every FET in the static decoder to be individually responsible for causing a state change at the decoder output. In this way, every FET within a set of SRAM address decoders may be tested for xe2x80x9cstuck-openxe2x80x9d faults. Both NAND and NOR logic functions, as shown above, typically appear in SRAM static address decoder circuits. By using static address decoders in SRAMs instead of dynamic decoders, the power consumption and switching-generated noise of the SRAM can be minimized. In the past, SRAM designs have frequently implemented static decoders despite this testability concern. The test pattern described herein will be able to detect all xe2x80x9cstuck-openxe2x80x9d faults in future SRAM circuits designs implementing CMOS static address decoders and prevent the faults from first being detected in the environment of the customer""s application.